Microsprings Having Nanowire Tip Structures

ABSTRACT

A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional application of copending U.S.Application for Letters Patent titled “Method of Producing MicrospringsHaving Nanowire Tips”, Ser. No. 11/963,507, filed on Dec. 21, 2007,which, in its entirety, is hereby incorporated herein by reference andto which priority is claimed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to photolithographicallypatterned spring contacts, and more particularly to a plurality of suchphotolithographically patterned spring contacts having nanowire tips,released at one end from a substrate such that the tips are oriented outof the plane of the substrate.

2. Description of the Prior Art

Photolithographically patterned spring devices (referred to herein as“microsprings”) have been developed, for example, to produce low costprobe cards, and to provide electrical connections between integratedcircuits. Such microsprings are disclosed and described, for example, inU.S. Pat. No. 5,914,218, which is incorporated by reference herein. Amicrospring is generally a micrometer-scale elongated metal structurehaving a free (cantilevered) portion which bends upward from an anchorportion which is affixed directly or indirectly to a substrate. Themicrospring is formed from a stress-engineered metal film (i.e., a metalfilm fabricated to have a stress differential such that its lowerportions have a higher internal compressive stress than its upperportions) that is at least partially formed on a release material layer.The microspring is attached to the substrate (or intermediate layer) ata proximal, anchor portion thereof. The microspring further includes adistal, tip portion which bends away from the substrate when the releasematerial located under the tip portion is removed (e.g., by etching).

The stress differential is produced in the spring material by one ofseveral techniques. According to one technique, different materials aredeposited in layers, each having a desired stress characteristic, forexample a tensile layer formed over a compressive layer. According toanother technique a single layer is provide with an intrinsic stressdifferential by altering the fabrication parameters as the layer isdeposited. The spring material is typically a metal or metal alloy(e.g., Mo, MoCr, W, Ni, NiZr, Cu), and is typically chosen for itsability to retain large amounts of internal stress. Microsprings aretypically produced using known photolithography techniques to permitintegration of the microsprings with other devices and interconnectionsformed on a common substrate. Indeed, such devices may be constructed ona substrate upon which electronic circuitry and/or elements havepreviously been formed.

FIGS. 1A-1C illustrate the basic, prior art process of fabricatingstress-engineered cantilevered microsprings 10. With reference first toFIG. 1A, stress-engineered cantilevers 10 are fabricated by depositingand patterning one or more films to form a stress-engineered cantilever12 with a designed strain-gradient over a sacrificial layer 14, whichitself is formed over a dielectric layer 16 pattered over a substrate18. Deposition conditions and other parameters may be controlled, asknown in the art, to tailor the stresses along the elevation (e.g., invarious layers) of the stress-engineered cantilever 12.Stress-engineered cantilever 12 can be of a single film type, such asMoCr alloy, where different layers of the film have different stresses.As stress-engineered cantilever 12 is initially formed in a plane whichis parallel to the primary plane of substrate 18, we refer to thefabrication of stress-engineered cantilever 12 as being “in-plane.”Stress-engineered cantilever 12 may also be composed of different filmtypes with different stresses. Stress-engineered cantilever 12 ispatterned and then released, as illustrated in FIG. 1B, by etching awaya portion of sacrificial layer 14 underneath the stress-engineeredcantilever 12. To lift the spring up and away from the substrate thestress gradient should be such that more compressive layers are disposedcloser to the substrate, and the more tensile layers disposed thereover.

After stress-engineered cantilever 12 is released, additional layers 20can optionally be plated on the surface of stress-engineered cantilever12, as shown in FIG. 1C, to improve strength and conductivity. Inadditional, multiple stress-engineered cantilevers 12 may be formed inan overlying relationship such that, for example, a lowerstress-engineered cantilever 12 provides structural support for an upperstress-engineered cantilever 12, as disclosed in the aforementioned U.S.patent application Ser. No. 11/292,474.

Stress-engineered cantilevers formed by this process are unique becausethe process facilitates the formation of arrays 22 of devices withcontact points out of the plane in which the devices are manufactured,as shown in FIG. 2. Linear and 2-d arrays can thereby be produced.Typically, array 22 is formed, with a tip-to-tip spacing selectedaccording to the application of the array. For example, for probetesting, the tip-to-tip spacing would match the spacing of contact pads,leads or the like on the device under test.

Another unique aspect of the process used to fabricate array 22 is thatthe stress-engineered cantilevers 12 are formed from thin films (e.g., 5um or less) in-plane, that is, in the same plane as the originalsubstrate. This is in contrast to processes used to produce, forexample, conventional silicon atomic force microscopy (AFM) tips, wherea tip is fabricated from a relatively thick film (10-20 microns),requiring expensive and complex 3D etching techniques, and where theetch sidewall profile strongly effects the shape tip of the tip of theAFM tip.

Such microsprings may be used in probe cards, for electrically bondingintegrated circuits, circuit boards, and electrode arrays, and forproducing other devices such as inductors, variable capacitors, scanningprobes, and actuated mirrors. For example, when utilized in a probe cardapplication, the tip of the free portion of a microspring is broughtinto contact with a contact pad formed on an integrated circuit, andsignals are passed between the integrated circuit and test equipment viathe probe card (i.e., using the microspring as an electrical contact).

Microsprings typically terminate at a tip, whose shape may be controlledphotolithographically as the microspring is pattered in-plane. Incertain applications, the microspring has a tip profile (e.g., an apicalpoint) capable of physically penetrating an oxide layer that may form onthe surface to which electrical contact is to be made. In order toprovide a reliable contact with a surface to be contacted, themicrospring must provide a relatively high contact force (the forcewhich the spring applies in resisting a force oppositely applied fromthe surface to be contacted). This is particularly true in applicationsin which the apical point must penetrate an oxide layer. For example,some probing and packaging applications require a contact force on theorder of 50-100 mg between the tip and the structure being contacted.

In certain applications, such as probe-based data storage, lithography,imaging, metrology, and printing and biology addition, there is a desireor requirement for extremely sharp microspring tips (<100 nm). In theseapplications lower forces are often used (<1 micronewton). Currentlithographic process have not proven sufficient to provide the desiredsharpness. There have been various attempts to provide very fine tipstructures in the prior art.

One approach to providing a very fine tip structure for a microspringhas been to manually bond a pre-formed nanowire onto the tip of areleased microspring. There are several known methods of producingnanowires.

Silicon nanowires—Chemical vapor deposition (CVD) has been widely usedto synthesize and grow large quantities of high quality siliconnanowires. The growth involves a vapor-liquid-solid process: vapor phaseprecursor (e.g., SiH4) decomposes on the surface of catalysts (e.g., Au)when heated up, and forms a liquid alloy. The continuous feeding of Siinto the alloy will supersaturate the alloy and Si nanowires will beginto grow elongate.

Silicon nanowires grow preferentially along the <111> direction throughepitaxial growth. If the vertical {111} planes are exposed, Si nanowires24 can grow horizontally, and bridge two opposite {111} planes, asillustrated in FIG. 3 (from R. He, D. Gao, R. Fan, A. I. Hochbaum, C.Carraro, R. Maboudian, and P. Yang, “Si Nanowire Bridges inMicrotrenches: Integration of Growth into Device Fabrication,” AdvancedMaterials, vol. 17, pp. 2098-2102, 2005). The density, diameter, andlength of the bridging Si nanowire 24 can be well-tuned by controllingthe density of catalyst, size of the catalyst, and the distance betweenthe two opposite planes. Growth temperatures are in the range of 400° C.and diameters are typically 10-20 nanometers (nm).

Germanium nanowires—The chemical vapor deposition (CVD) growth strategyfor germanium nanowires is very similar to silicon nanowires, which alsofollows a vapor-liquid-solid process, except that a gas phase precursorwill be a germanium-containing gas, such as GeH4 instead of SiH4, and ingeneral the growth temperature will be lower than Si nanowire growth(approximately 300° C.). Typical diameters are 10-40 nanometers (nm).

Carbon nanotubes—Growth of nanometer-scale structures in carbon producea unique, hollow or tube-like structure. Accordingly, such structuresformed of Carbon are commonly referred to as nanotubes. For carbonnanotube growth, CVD growth is also one of the best synthesis methods.The gas phase precursors are carbon containing gases, such as CH4, C2H4,C2H5OH vapor etc; metal catalysts are usually Fe, Co, Ni etc instead ofAu for Si and Ge nanowires. Typical growth temperatures areapproximately 650° C. and of diameter less than 3 nm.

Nanotubes spread out on a substrate can be placed onto a silicone AFMtip by using micromanipulators. Nanotubes manually attached to probetips are available as “CNTek carbon nanotube-tipped AFM probes” fromNanoscience Instruments, Inc. (www.nanoscience.com). For manyapplications, such probes are prohibitively expensive. Furthermore,production of arrays are not practical with this method because theassembly process is insufficiently repeatable in terms of nanotubeposition and length. In general, given the very small size of thesestructures, accurately positioning and bonding the nanowire onto the tipof a probe has proven challenging.

Another effort at providing integrated nanowires and microspringsinvolves growth of nanowires on conventional cantilever tips. Growth ofcarbon nanotubes on a probe structure has been attempted with usingchemical vapor deposition where the catalyst is patterned on the side ofan existing silicon etched probe tip. It is asserted that this processproduces nanotubes protruding on 90% of an array of probe tips on awafer, extending 1-10 micrometers beyond the silicon tip. However, thisnon-uniformity has prohibited use of these structures, as grown, forprobing applications. To shorten the nanotubes to sub-1 micrometerextension, an oxidation discharge process has been employed, whichnecessitates handling each single cantilever in a tapping modeelectrical AFM mode setup. Similar to the gluing, the process isessentially serial, and prohibitive in terms of cost, time, andultimately uniformity.

Field enhanced growth has also been used for nanometer-scale tipproduction, such as growing tungsten nanowires seeded from metal pads ina tungsten vapor ambient. The process is serial (one tip at a time),cumbersome, and requires precise alignment of a sharp tip counterelectrode close to the silicon tip. Nonetheless, nanowires on the endsof silicon tips have been fabricated and used in probing experiments.

Focused ion beam etching and electron beam induced deposition have alsobeen used to produce devices having micromachined nanometer-scale tips,referred to herein as nanotips. Each of these techniques attempts toplace a nanowire or nanotube perpendicularly at the micromachined tip ofan in-plane probe structure. However, such processes suffer from lowuniformity, control, yields, and throughputs due to the difficulty ofvertically aligning the nanowires (both in length and in angle relativeto the plane of the probe).

What is needed is a way to make nanowires or equivalently, nanotubes, oncantilevers in a parallel process such that two dimensional arrays ofuniform nanotips can be readily formed.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method ofmanufacturing a of stress-engineered, cantilevered microspring having ananowire tip, and to a microspring and an array of microsprings soformed. Nanowires (as used herein including both solid structures andhollow or nanotube structures) are grown generally in-plane with thesubstrate at the tips of the microsprings prior to release of themicrosprings from the substrate. Controlled geometry of the nanowiresmay therefore be provided by standard growth and patterning processes.The microsprings with nanowire tips may then be released from thesubstrate, causing the microspring tips and hence the nanowire tips topoint up, out of the plane of the substrate, due to a relaxing stressgradient. The nanowires may be in electrical communication with themicrosprings facilitating the use of the nanowires as contacts, probetips, and the like. This approach significantly simplifies theintegration of uniform nanowires into probe based applications.

According to one aspect of the invention, the basic steps of providing amicrospring having a nanowire tip comprise:

Defining a stress-engineered cantilever and appropriate growthboundaries in-plane

Defining the nanowire catalyst/seed layers

Growth of the nanowires with good control and uniformity

Release the stress-engineered cantilever and the nanowire, forming ananotip array

According to another aspect of the present invention, uniform nanowirelength can be provided by photolithographically defining a mask whichprotects a selected length of the grown nanowire from etching. That is,portions of the nanowire not protected by the mask may be removed forexample by etching. Length of the nanowire may then be controlled up tothe resolution of the lithographic masking process.

According to another aspect of the present invention, a nanowire grownat the tip of a microspring may be clamped at the point of attachment ofthe nanowire to the microspring to provide improved robustness. Thisclamping may be accomplished by deposition and patterning of a thin-filmlayer, taking advantage of the processes and orientation used to formthe microspring and nanowire.

According to still another aspect of the present invention, a fieldenhancement process may be employed to facilitate nanowire growth.Electrodes may be formed of the material ultimately forming themicrospring. A potential between these electrodes assists withdirectionality, thickness, and other attributes of the grown nanowire.

According to yet another aspect of the present invention, catalyst sitesfor nanowire growth may be deterministically provided on the surface ofthe microspring. While this results in some out-of-plane growth of ananowire, the nanowire may be coaxed in-plane, if necessary, and held inplace by a clamping structure, again for example photolithographicallydefined.

According to a still further aspect of the present invention, themicrospring and the nanowire may be separately and independentlyfabricated, then joined together such that the nanowire extends out ofplane upon release of the microspring. The nanowire is preferablyattached to the microspring prior to spring release, but mayalternatively be attached after release. A clamping structure mayoptionally be employed to improve the robustness of the mechanicalconnection between the nanowire and the microspring. The nanowire may beattached to the microspring either on the face of the microspring or ona sidewall of the microspring.

Finally, according to still another aspect of the present invention, thenanowire at the tip of the microspring may be coated with a material toobtain a desired functionality. For example, electrical junctions may beformed on the surface of the nanowire. Or, the nanowire may be coated ina biological material, as may be appropriate for nanometer-scalesensing, drug delivery, etc.

The above is a summary of a number of the unique aspects, features, andadvantages of the present invention. However, this summary is notexhaustive. Thus, these and other aspects, features, and advantages ofthe present invention will become more apparent from the followingdetailed description and the appended drawings, when considered in lightof the claims provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings appended hereto like reference numerals denote likeelements between the various drawings. While illustrative, the drawingsare not drawn to scale. In the drawings:

FIGS. 1A through 1C are illustrations of a prior art process forfabrication of a microspring.

FIG. 2 is a micrograph of an array of microsprings released from asubstrate according to the prior art.

FIG. 3 is a nanowire grown between exposed faces of a seed structureaccording to the prior art.

FIG. 4 is a table illustrating the wear characteristics of two differentprofiles of nanotips for probe applications.

FIGS. 5A and 5B are an elevation view and a plan view, respectively, ofa first step in the process of producing a microspring having a nanowiregrown in situ at the tip thereof according to an embodiment of thepresent invention.

FIGS. 6A and 6B are an elevation view and a plan view, respectively, ofthe step of providing catalyst sites for the growth of nanowires in theprocess of producing a microspring having a nanowire grown in situ atthe tip thereof according to an embodiment of the present invention.

FIG. 6C is an elevation view of the step of providing catalyst sitesfrom the growth of nanowires, including the limiting of growth ofnanowires on selected surfaces by the application of a fouling layer inthe process of producing a microspring having a nanowire grown in situat the tip thereof according to an embodiment of the present invention.

FIGS. 7A and 7B are an elevation view and a plan view, respectively, ofthe step of growing a nanowire in the process of producing a microspringhaving a nanowire grown in situ at the tip thereof according to anembodiment of the present invention.

FIGS. 8A and 8B are an elevation view and a plan view, respectively, ofthe step of masking and defining the nanowire length (and elimination ofextraneous secondary nanowires) in the process of producing amicrospring having a nanowire grown in situ at the tip thereof accordingto an embodiment of the present invention.

FIGS. 9A and 9B are an elevation view and a plan view, respectively, ofthe release step in the process of producing a microspring having ananowire grown in situ at the tip thereof according to an embodiment ofthe present invention.

FIGS. 10A and 10B are an elevation view and a plan view, respectively,of the step of forming a clamping structure at the junction of amicrospring tip and nanowire in the process of producing a microspringhaving a nanowire grown in situ at the tip thereof according to anotherembodiment of the present invention.

FIGS. 11A and 11B are an elevation view and a plan view, respectively,of the release step in the process of producing a microspring having ananowire grown in situ at the tip thereof according to the process shownin FIGS. 10A and 10B.

FIGS. 12A and 12B are an elevation view and a plan view, respectively,of the step of field enhanced growth of a nanowire at the tip of amicrospring in the process of producing a microspring having a nanowiregrown in situ at the tip thereof according to yet another embodiment ofthe present invention.

FIGS. 13A and 13B are an elevation view and a plan view, respectively,of the step of controlled catalyst site growth of a nanowire out ofplane at the tip of a microspring in the process of producing amicrospring having a nanowire grown in situ at the tip thereof accordingto still another embodiment of the present invention.

FIGS. 14A and 14B are an elevation view and a plan view, respectively,of the step of clamping in-plane a nanowire grown out of plane at thetip of a microspring in the process of producing a microspring having ananowire grown in situ at the tip thereof according to the embodimentshown in FIGS. 13A and 13B.

FIGS. 15A and 15B are an elevation view and a plan view, respectively,of the release step in the process of producing a microspring having ananowire grown in situ at the tip thereof according to the process shownin FIGS. 14A and 14B.

FIG. 16 is a perspective view of a portion of a nanowire showing aselected coating applied to a portion thereof according to yet anotherembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

We next present a description of several embodiments of the presentinvention. The specific requirements for these embodiments vary byapplication, but probe array requirements for data storage applicationsare fairly representative of other applications.

-   -   Requirement for probe based data storage include:    -   fine tip resolution (<100 nm, with <30 nm preferred)    -   robust tips (don't wear, tip stays sharp, consistent position)    -   uniform tip heights to facilitate alignment to the substrate        (height deviation within several microns)    -   high yield fabrication process (for 100s to thousands of probes)    -   adequate conductivity of nanotips

Sharp tips enable small data bits to be written and read—18 nanometerpitches and 2 terabits/in² have been demonstrated. Equally importantthough, is the sharpness as a function of time. Inevitably the tipswear—especially for the approaches which uses a hard media substrate.High aspect ratio tips are advantaged because the radius tends to staysmall as the tip wears (FIG. 4). Nanotips can be higher aspect ratiothan traditional bulk silicon etched based tips. Because the media isnot patterned, the tips do not have to be perfectly straight andperfectly vertical from the substrate. However they do need to besufficiently uniform to be able to repeatedly contact the same spot sothat they can read a bit after writing it (media is initiallyunpatterned, and the writing and reading tips are usually the same). Inaddition the bit size should be sufficiently uniform, which could dependon multiple factors such as tip radius and force. The force uniformityrequirements, for a given cantilever, can translate into a heightuniformity requirement. Ideal requirements are force variation of lessthan 10 nano-Newtons (nN) and tip radius of less than 20 nanometers(nm), with small tip height variation (on the order of severalmicrometers or less, depending on cantilever probe stiffness).

The tip fabrication process should be readily integrated with thecantilever process. The yield needs to be extremely high, but slightdeviations from 100% can be corrected in software and planned for withredundancy. Finally the electrical conductivity of the tip should beappropriate for the writing/reading mechanism. Normally the bulk siliconbased tips are not doped for lower conductivity, but if needed thenanotips wires could be doped.

According to the present invention, nanowires or nanotubes arefabricated parallel to the substrate at the tips of in-plane fabricatedstress-engineered cantilevers. The stress-engineered cantilevers pullthe nanotip out of the plane when released. The nanowire can then begrown parallel to the surface of a substrate, so that multipleprocessing techniques can be used to control growth uniformity.

The basic steps of a first embodiment of the present invention include:

-   -   Define the stress-engineered cantilever    -   Define the nanowire catalyst/seed layers    -   Grow the nanowires with good control and uniformity    -   Release the stress-engineered cantilever and the nanowire,        forming a nanotip array

With reference initially to FIGS. 5A and 5B, there is shown therein anddescribed below a basic process for integrating silicon nanowires onto astress engineered cantilever. The process begins with the deposition ofa sacrificial layer 32 over a silicon, glass, quartz or a polymer suchas polyimide substrate 30. Release layer 32 is formed of materials knownand used in stressed metal applications, such as Ti, Ni, SiO2, SiN,SiOxNy or Si. Optionally, substrate 30 may have previously formedthereon electronic components and/or circuitry (not shown), oralternatively substrate 30 may be a printed circuit board or printedwiring board. An optional insulating underlayer (not shown) may bedeposited and patterned in applications in which electrical insulationis desired between the microspring and other elements of the finalplural microspring structure.

A stress-engineered material system 34 is next deposited over thestructure, then photolithographically patterned. Ultimately, materialsystem 34 becomes a microspring when released. According to oneembodiment, material system 34 comprises prior to release two spacedapart regions 34 a, 34 b, which are photolithographically formed andwhich will be used for the growth of a nanowire or nanotubetherebetween. Accordingly, material system 34 may be any of a variety ofmetals or alloys suitable for the creation of microsprings, such as Mo,MoCr, W, Ni, NiZr, Cu (or a non metal). Material system 34 can also becomposed of a low stress single crystal silicon layer and a high stresslayer, tensile or compressive. The (111) plane of single crystal siliconhas been shown to provide a high yield for growing in-plane nanowires(normal to the sidewalls). This system is illustrate in FIG. 3. Astress-engineered layer such as silicon nitride can be used to pull thesilicon layer up during the release.

Material system 34 is deposited in such a way as to develop within thelayer a stress differential in a vertical direction across the layer'scross-section. That is, the stress in the system varies from bottom totop. According to one embodiment, material system 34 comprises a singlelayer of material, and the gas pressure or power is varied during thedeposition process to create a stress-engineered single layer (i.e., alayer comprised of a single material) having a desired cross-sectionalstress differential. According to another embodiment (not shown),material system 34 is itself comprised of a number of sub-layers, eachsub-layer having a desired intrinsic stress. When properly selected, theassembly of sub-layers mechanically and electrically functions as asingle system, but the bulk stress differential across the system oflayers is a composition of the individual stresses of the sub-layers.These techniques are further described in U.S. Pat. No. 5,613,861, andU.S. Pat. No. 5,914,218 which are incorporated by reference herein.While formed in a plane, the result of the stress in system 34 is thatwhen the layer is patterned into a microspring structure, two regionsare formed. A first, proximal, anchor region attaches the microspring tothe substrate (or an intermediate layer over the substrate), and asecond, distal, tip region is released from the substrate by removal ofa portion of release layer 32. When released, the tip region of themicrospring bends out of plane, resulting in a non-planar microspringprofile having a desired spring constant. The released structure isdiscussed further below.

Various combinations of stress engineered layers and nanotips arepossible, but the compatibility of the process temperatures needs to beconsidered. For example, silicon or germanium nanowires can be grownabove metal stress-engineered layers as long as the temperatures do notanneal out the stress, meaning an effective limit of approximately 400 Cor less. Carbon nanotube manufacturing is typically at much highertemperatures, on the order of 700 C, so the stress engineered layer maybe further deposited (or alternatively, deposited in whole) after thenanotube growth. Alternatively, material from which stress-engineeredmaterial system 34 is formed should be a high temperature film like atensile nitride.

According to one embodiment, the single crystal silicon can be purchasedas the top layer of an SOI (silicon-on-insulator) wafer, which has thinsilicon and thin oxide on a thick substrate. The in-plane cantileverstructure can be patterned with standard photolithography and etchingtechniques.

With reference next to FIGS. 6A and 6B, the next step is to depositnanometer scale metal dots 40 to serve as growth seed (catalyst) sitesand to define the diameter of the nanowire to be formed. One method isto flow a solution containing nanodots 40 over a prepatterned liftoffmask 42. Commercially available nanodot solutions include gold particles10s of nm diameter. (See www.Aldrich-Sigma.com; www.tedpella.com.) Theconcentration of particles should be high enough so that one or moreparticles attaches to the sidewall of the cantilever tip. The liftofflayer (such as photoresist) is then removed to remove unwanted andunneeded seed dots from the structure.

According to a variation of this embodiment, the catalyst sites at thelocations of nanodots 40 may be “poisoned” to selectively suppressnanowire growth. As illustrated in FIG. 6C, a fouling layer 44 may beformed on surfaces of the stress-engineered material system to poisonthe catalyst thereover. Molybdenum, for example, is known to preventnanowire growth from gold seed dots. A thin layer of patterned Mo may bedefined such that only areas of portions 34 a and 34 b between whichnanowire growth is desired are exposed. Accordingly, layer 44 may becomprised of Mo or an Mo alloy. Nanowire growth in all but the regionson layer 44 is thereby limited. If the fouling layer 44 is on the topsurface of 34A and 34B but not on the sidewalls, then growth ofnanowires should preferentially occur on the sidewalls over the topsurface of 34A and 34B. In FIG. 6C the nanodot 40′ on the sidewall of34B is not under a fouling layer 44 and is thus the most likely placefor nanowire growth to occur.

With reference to FIGS. 7A and 7B, nanowires 46 a, 46 b are next grown.While growth of nanowires is well known in the art, in one embodiment ofthe present invention silicon wires may be grown, driven by a vaporphase precursor (using a chemical vapor deposition process), initiatingfrom the gold dots 40 on the (111) sidewalls of the microspring tip.Ideally one wire, primary nanowire 46 a, grows from each microspringsidewall, and the growth stops when it hits the opposing boundaryregion. However, it may be common that extraneous secondary nanowires,such as such as nanowires 46 b, will grow from dots of various exposedsidewall portions of the microspring. Many aspects of the final nanowiremay be controlled at this stage, such as the diameter of the wire,tensile properties of the nanowire, etc. It is noted that the growth ofnanowires 46 are such that they are in electrical communication withstress-engineered material system 34 so that when stress-engineeredmaterial system 34 is released to form a microspring the nanowire mayform an electrically conductive tip of the microspring.

With reference next to FIGS. 8A and 8B, a mask layer 50 may then beapplied over the structure, and patterned in order to protect themicrospring and a portion of nanowire 46 a (and portions of wires 46 b).Etching may then be performed to remove any exposed material, such asexposed portions of nanowires 46 a, 46 b, as well as the exposed portion34 b of stress-engineered material system 34. It will be noted that thisetching step also effectively removes any extraneous secondary nanowires46 b. Note also that this step lithographically defines the length (andhence aspect ratio) of primary nanowire 46 a, permitting very controlledand uniform nanowire length for an array of such nanowires, overcomingthe uniform length problem present in many prior art efforts to providenano-scale probe tips.

With reference to FIGS. 9A and 9B, mask layer 50 is removed for exampleby a solvent process. Sacrificial release layer 32 is next etched andportion 34 a of stress-engineered material system 34 is undercut,releasing a portion 34 a and thereby forming a microspring 54. Theinternal stress gradient lifts the microspring 54 out of the plane,taking with it the nanowire 46 a.

In this embodiment, the vertical (i.e., out of plane) nanotip propertiesare controlled though multiple mechanisms which are applied while themicrosprings are being fabricated in-plane. Such control has heretoforenot been possible, particularly as a complete set of attributescontrollable as part of a single manufacturing process. Specifically,the following attributes may be process-controlled:

-   -   Nanowire axis direction—this attribute may be controlled by        selection of the crystal plane to be exposed as the microspring        sidewall, electric field guided, fluidics to steer assembly.    -   Nanowire length (axial)—this attribute may be controlled by the        size of the gap photolithographically formed between sections 34        a and 34 b of the stress engineered material system 34 and by        the masking and etching steps following growth of the nanowire.    -   Number of nanowires in an array—this attribute may be controlled        by the patterning of stochastically deposited nanodots (catalyst        sites), or in an alternate embodiment, by deterministic        patterning of seed layers (described further below), and by the        masking and etching steps following growth of the nanowire.    -   Size of the nanowires—this attribute may be controlled by the        size of the deposited nanodots which act as catalyst sites for        nanowire growth, or in an alternate embodiment, by high        resolution patterning of the catalyst layer.    -   Robustness of the nanowires—this attribute is provided by the        robustness of the connection at the growth site of the nanowire        (attachment at a growth site tends to be more robust than        attachment at a point of adhesion of a separately formed        nanowire), the control over the nanowire aspect ratio as part of        the growth process, and the control of nanowire length by the        masking and etching steps following growth of the nanowire.    -   Functionality of the nanowires—this attribute may be controlled        by the pattern-wise dope, coat with polymers, or bio-coated        particles.

There are many alternative embodiments which have important advantagesand applications. According to a first such alternative embodiment,shown in FIGS. 10A, 10B, 11A and 11B, a clamping structure 56 is formedat the junction of the microspring tip and the nanowire for strength.With reference to FIGS. 10A and 10B, which show elevation and planviews, respectively, of a structure in the process of being produced,clamping structure 56 may be comprised of a material such as platinum orgold and is deposited with standard techniques like sputtering orplating, and readily patterned with etching or liftoff techniques suchthat it encases the junction between portion 34 a of stress-engineeredmaterial system and nanowire 46 a. This deposition and patterning takesplace advantageously prior to release of portion 34 a ofstress-engineered material system from sacrificial layer 14. Improvedadherence of nanowire 46 a to the microspring formed on release ofportion 34 a is obtained. FIGS. 11A and 11B show the final structureincluding microspring 54, nanowire tip 46 a, and clamping structure 56in elevation and plan views, respectively.

It should be noted that in the foregoing, regions 34 a and 34 b werecomprised of the same material. It will be appreciated however, thatregions 34 a and 34 b may alternatively be comprised of differentmaterials and/or formed at different times. For example, an oxide layercould serve as a boundary stop region 34 b and have the advantage thatit would etch away with the release layer, reducing the number of steps.Such an oxide material may in fact be the same material as sacrificialrelease layer 32. Indeed, it is possible to grow nanowires from the tipregion of portion 34 a without a corresponding region 34 b (hence,region 34 b is shown in dashed outline), with masking and etching aspreviously described to control the direction, size, and number ofnanowires.

Furthermore, it should be noted that in the prior description nanowire46 was grown such that it extends between the sidewalls of regions 34 aand 34 b. However, the nanowire may, in fact, grow from the uppersurface of region 34 a (as opposed to the sidewall), to either thesidewall or upper surface of region 34 b, or from the sidewall of region34 a to the upper surface of region 34 b. It is therefore apparent thatthe long axis of the nanowire may vary a certain degree from beingperfectly parallel with the plane of the substrate. Furthermore, thenanowire itself may not be linear at all. In these cases, the nanowireis said to generally extend in the direction of the plane of thesubstrate, with the important aspect being that upon release of themicrospring, the nanowire presents its tip for desired contact ratherthan the tip of the microspring. Typically this means that the tip ofthe nanowire extends farther above the surface of the substrate than thetip of the microspring.

According to another embodiment of the present invention, an in-planefield enhanced structure is used to guide nanowire growth. Such anembodiment in the process of production, is shown in elevation view inFIG. 12A and in plan view in FIG. 12B. Planar processing and etchingtechniques are be used to form portion 34 b of stress-engineeredmaterial system 34 as a sharp counter electrode 60 to guide growth ofthe nanowire 46 a. Such a lithographically aligned counter electrode 60can be connected so that a single electrode controls growth over theentire wafer. For example, portion 34 a may be electrically grounded,while a potential applied to electrode 60, resulting in guided growth ofthe nanowire 46 a in the direction of arrow A. As with theprior-described embodiments, counter electrode 60 can be removed afternanowire growth (by masking and etching) to allow for the release of thecantilever and lifting of the nanotip. In some applications the counterelectrode 60 does not have to be removed, and can remain a permanentpart of the final device.

According to still another variation of the present invention, thecatalyst sites (locations of nanodots 40) can be patterned directly byassembling nanodots in a solution with liftoff, or with masking ofnanostructured substrates (such as iron nanoparticles in mesoporoussilica). However, as this is still a stochastic process which willultimately limit yield. Direct patterning of a catalyst is alsoapplicable for integration with stress engineered devices. Electron beamlithography represents one method which may be used to pattern ananometer scale dot (20-50 nm in diameter). Microcontact printing anddip pen lithography are alternate methods for patterning. Optimizedgrowth conditions can lead to single wire/tube growth for each catalystsite. With reference to FIG. 13A, which is an elevation view, and FIG.13B, which is a plan view, according to one aspect of this embodiment,the catalyst sites are patterned on the top surface of portion 34 a ofthe stress-engineered material system. Nanowire 64 is then grownvertically from a catalyst site, such as patterned nanodot 66. Looselyadhered nanowires, such as nanowire 64, are controllably tipped overwith fluidic force, such as by an directed gas stream, and then clampedby a clamping structure 68 onto stress-engineered material systemportion 34 a, as illustrated in FIGS. 14A and 14B. A masking layer 70may be deposited and patterned over the structure to define the finallength of nanowire 64 as previously described. The final releasedstructure is illustrated in FIGS. 15A and 15B, which are unique in thatnanowire 64 is rooted on microspring 54 not at a sidewall of the later,but rather on a planar surface thereof.

According to another embodiment described herein, functionalizednanotips, as illustrated in FIG. 16, may be provided at the tips of themicrosprings. Following growth of nanowire 80, a coating may meselectively applied to a portion thereof, such as distal portion 82,leaving the remainder 84 of nanowire 80 uncoated. The coating may beapplied by way of a standard thin film or other appropriate process. Ahorizontally grown nanowire or nanotube can thereby be readilyfunctionalized for a sensing or biochemical application. For example,part of the tip can be doped to form an electronic heterojunction formeasuring a specific chemical concentration such as proton concentration(pH) or the like. Furthermore, biological coatings may be applied to thenanowire, or nanoparticles can be attached to well defined portions ofthe nanowires, for sensing or drug delivery on a nanometer scale.

According to a final embodiment of the present invention, prefabricatednanowires may be attached to prefabricated microsprings in-plane, priorto release of the microsprings from the substrate. According to thisembodiment, the microsprings are formed as previously described. In onevariation, first region 34A and possibly second region 34 b are formed(e.g., FIG. 5A). Individual single or multiwall carbon nanotubes ornanowires in solution may then be assembled between portions 34 a and 34b using Langmuir-Blodgett film monolayer protocols. A Langmuir-Blodgettfilm can be made by floating nanowires or carbon nanotubes on watersurface inside a teflon trough with pressing bars. When the bars arepressed, the floating nanowires or carbon nanotube will be assembled andaligned. The nanowire or carbon nanotube assembly direction can bealigned with the microspring long axis direction so that nanowires orcarbon nanotube can be attached to the microspring tips with the desiredorientation. (See, D. Whang, S. Jin, Y. Wu and C. M. Lieber,“Large-Scale Hierarchical Organization of Nanowire Arrays for IntegratedNanosystems,” Nano Lett. 3, 1255-1259 (2003)).

According to another variation of this embodiment, surface energytechniques can be used to assemble pre-fabricated nanowires. A patternedhydrophilic film on a cantilever tip region (such as 34A) would attractnanowires in solution to that region. Self assembled monolayers can beused to control the surface energy. See for example see S. Liu, J. B-H.Tok, J. Locklin Z. Bao, “Assembly and Alignment of Metallic Nanorods onSurfaces with Patterned Wettability”, Small, Vol. 2, No. 12, p.1448-1453, 2006; B. R. Martin, S. K. St. Angelo, T. E. Mallouk,“Interactions Between Suspended Nanowires and Patterned Surfaces”,Advanced Functional Materials, Vol 12, No. 11-12, pp. 759-765, 2002.

According to still another variation of the present embodiment,dielectrophoretic or electrophoretic forces are used to assemble singletubes and grow them between regions 34 a, 34 b. An electric fieldbetween two patterned conductive regions (such as 34A, 34B) can be usedto assemble pre-fabricated nanowires in a controlled manner. Forexample, an alternating electric field across a gap can assemble carbonnanotubes using diaelctrophoretic forces; see “L. A. Nagahara, I.Amlani, J. Lewenstein, R. Tsui, “Directed placement of suspended carbonnanotubes for nanometer-scale assembly”, Vol. 80, No. 20, pp. 3826-3828,2002). Similarly, electrophoretic forces can be used to assemble ananowire which has its own electric charge. A constant electric fieldbetween two conductors, such as 34A and 34B could be used direct such ananowire onto the tip region of the cantilever. The nanowires follow theelectric field lines, so they could be directed to assemble in adesigned direction with respect to the cantilever tip region 34A. If thenanowire had a positive charge on one side and a negative charge on theother, the positive end would go to the negative voltage electrode(could be 34A) and the negatively charged end of the nanowire would movetowards the positive voltage electrode (could be 34B).

In still another variation, microfluidic channels are used forassembling bundles of nanotubes or nanowires. This microfluidic methodhas been demonstrated to align nanowires with good control. Siliconemode form channels are used to allow a solution containing nanowires topass therethrough. Some nanowires will be aligned when passing throughthe channels, and attach to the substrate. The flow direction may bealigned with the long axis of the microsprings, and the alignednanowires thereby attached with the desired orientation. (See, Y. Huang,X. Duan, Q. Wei, and C. M. Lieber, “Directed Assembly of One-DimensionalNanostructures into Functional Networks,” Science 291, 630-633 (2001)).

Regardless of the technique used to manipulate the nanowires on themicrosprings, once the nanowires are satisfactorily placed, a clampinglayer may be applied in order to secure the nanowires in place, and thestructure may be masked and etched to remove undesirable nanowires, tocontrol the length of the nanowires, to release the microspring, toremove the region 34 b, etc., as previously described. A microspringcurving upward out of the plane of the substrate having one or morenanowires of desired length and orientation is obtained. An array ofsuch devices may just as easily be obtained.

While a plurality of preferred exemplary embodiments have been presentedin the foregoing detailed description, it should be understood that avast number of variations exist, and these preferred exemplaryembodiments are merely representative examples, and are not intended tolimit the scope, applicability or configuration of the invention in anyway. For example, the majority of the embodiments described above havefocused on the production of a single nanowire at the tip of amicrospring. However, it is entirely within the scope of the presentinvention to produce a structure having a plurality of such nanowires atthe tip of the microspring, depending solely on the intended applicationof the structure so obtained. Furthermore, the description hereinillustrates the production of a single microspring with nanowire formedthereon. However, any of the embodiments described herein may produce anarray of such devices. The array may be a linear array (tips aligned ina single row), a two-dimensional array (tips varying in two dimensionsin a plane above the substrate), or other suitable arrangement as afunction of the intended application of the array. Therefore, theforegoing detailed description provides those of ordinary skill in theart with a convenient guide for implementation of the invention, by wayof examples, and contemplates that various changes in the functions andarrangements of the described embodiments may be made without departingfrom the spirit and scope of the invention defined by the claimsthereto.

1. A spring contact, comprising: a substrate; a stress-engineered memberhaving an anchor portion and a free portion, the anchor portion fixed tothe substrate and substantially extending in a first plane, the freeportion not fixed to the substrate and extending out of and not parallelwith the first plane; a nanowire formed on the free portion andextending out of and not parallel with the first plane; wherein thestress-engineered member as-formed is provided with an inherent stressgradient in a direction substantially perpendicular to the first plane,said nanowire initially formed on and in electrical communication withthe free portion, and the free portion released from the substrate suchthat the inherent stress gradient in the stress-engineered member biasesthe free portion away from the substrate carrying with it the nanowire.2. The spring contact of claim 1 wherein said stress-engineered memberis formed to have a sidewall extending substantially perpendicular tosaid first plane, and said nanowire is formed on said sidewall.
 3. Thespring contact of claim 2, wherein said stress-engineered membercomprises a stress engineered layer over a single-crystal silicon layersuch that said sidewall presents the <111> plane of said single crystalsilicon in the region in which said nanowire is formed on said sidewall.4. The spring contact of claim 1, wherein said nanowire has a tip which,following release of the free portion of said stress-engineered member,extends above said substrate by a distance greater than the greatestdistance said free portion extends above said substrate.
 5. The springcontact of claim 1, wherein each of the stress-engineered member and thenanowire have a primary long axis, and further wherein each said primarylong axis is generally parallel to the other.
 6. The spring contact ofclaim 1, further comprising a clamping structure formed over and aroundat least the point of connection between the stress-engineered memberand the nanowire.
 7. The spring contact of claim 6, wherein saidnanowire originally extends out of and not parallel with said firstplane, and further wherein said nanowire is bent and clamped by saidclamping structure into said first plane prior to release of said freeportion.
 8. The spring contact of claim 1, wherein at least a tipportion of said nanowire has a coating applied thereto.
 9. The springcontact of claim 1, wherein at least a tip portion of said nanowire isdoped.
 10. The spring contact of claim 1, further comprising a pluralityof nanodots applied as a coating over said microspring body, and whereinsaid nanodots form catalyst sites from which said nanowire forms. 11.The spring contact of claim 10, wherein said nanowire originally extendsout of and not parallel with said first plane, and further wherein saidnanowire is bent and clamped by a clamping structure into said firstplane prior to release of said free portion.